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| SERIAL PRESENCE DETECT PC100 Unbuffered DIMM PC100 Unbuffered DIMM(168pin) SPD Specification(128Mb C-die base) Rev. 0.1 Apr. 2000 Rev 0.1 Apr. 2000 SERIAL PRESENCE DETECT M366S1724CT0-C1H/C1L * Organization : 16Mx64 * Composition : 8Mx16 *8 * Used component part # : K4S281632C-TC1H/C1L * # of rows in module : 2 Rows * # of banks in component : 4 banks * Feature : 1,375mil height & double sided component * Refresh : 4K/64ms * Contents ; Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 10ns 6ns Non parity PC100 Unbuffered DIMM Function Supported -1H 128bytes 256bytes (2K-bit) SDRAM 12 9 2 Rows 64 bits LVTTL 10ns 6ns A0h 60h -1L -1H Hex value -1L 80h 08h 04h 0Ch 09h 02h 40h 00h 01h A0h 60h 00h 80h 10h 00h 01h 8Fh 04h 06h 01h 01h 00h Note 1 1 2 2 15.625us, support self refresh x16 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 10ns 6ns 20ns 20ns 20ns 50ns 12ns 7ns 20ns 20ns 20ns 50ns A0h 60h 00h 00h 14h 14h 14h 32h 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time 0Eh C0h 70h 00h 00h 14h 14h 14h 32h 10h 20h 10h 20h 20h 10h 20h 2 2 2 Rows of 64MB 2ns 1ns 2ns 2ns 1ns 2ns Rev 0.1 Apr. 2000 SERIAL PRESENCE DETECT Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, # of banks in Comp. & interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations 1 H Blank 0 -1H 1ns - PC100 Unbuffered DIMM Function Supported -1L 1ns -1H 10h 00h 12h 0Eh CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 31h 37h 32h 34h 43h 54h 30h 2Dh 43h 1 L 31h 48h 20h 30h 43h 64h FFh FDh 5 3 3 4 5 31h 4Ch 3Eh Hex value -1L 10h Note PC100 SPD Spec. Ver. 1.2A Samsung Samsung Onyang Korea M 3 Blank 6 6 S 1 7 2 4 C T 0 "-" C C-die (4th Gen.) Undefined 100MHz Detailed 100MHz Information Undefined Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung s own purpose. Rev 0.1 Apr. 2000 SERIAL PRESENCE DETECT M366S3323CT0-C1H/C1L * Organization : 32Mx64 * Composition : 16Mx8 *16 * Used component part # : K4S280832C-TC1H/C1L * # of rows in module : 2 Rows * # of banks in component : 4 banks * Feature : 1,375mil height & double sided component * Refresh : 4K/64ms * Contents ; Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 10ns 6ns Non parity PC100 Unbuffered DIMM Function Supported -1H 128bytes 256bytes (2K-bit) SDRAM 12 10 2 Rows 64 bits LVTTL 10ns 6ns A0h 60h -1L -1H Hex value -1L 80h 08h 04h 0Ch 0Ah 02h 40h 00h 01h A0h 60h 00h 80h 08h 00h 01h 8Fh 04h 06h 01h 01h 00h Note 1 1 2 2 15.625us, support self refresh x8 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 10ns 6ns 20ns 20ns 20ns 50ns 12ns 7ns 20ns 20ns 20ns 50ns A0h 60h 00h 00h 14h 14h 14h 32h 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock@CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock@CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time 0Eh C0h 70h 00h 00h 14h 14h 14h 32h 20h 20h 10h 20h 20h 10h 20h 2 2 2 Rows of 128MB 2ns 1ns 2ns 2ns 1ns 2ns Rev 0.1 Apr. 2000 SERIAL PRESENCE DETECT Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, # of banks in Comp. & interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations 1 H Blank 0 -1H 1ns - PC100 Unbuffered DIMM Function Supported -1L 1ns -1H 10h 00h 12h 17h CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 33h 33h 32h 33h 43h 54h 30h 2Dh 43h 1 L 31h 48h 20h 30h 43h 64h FFh FDh 5 3 3 4 5 31h 4Ch 47h Hex value -1L 10h Note PC100 SPD Spec. Ver. 1.2A Samsung Samsung Onyang Korea M 3 Blank 6 6 S 3 3 2 3 C T 0 "-" C C-die (4th Gen.) Undefined 100MHz Detailed 100MHz Information Undefined Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung s own purpose. Rev 0.1 Apr. 2000 SERIAL PRESENCE DETECT M374S3323CT0-C1H/C1L * Organization : 32Mx72 * Composition : 16Mx8 *18 * Used component part # : K4S280832C-TC1H/C1L * # of rows in module : 2 Rows * # of banks in component : 4 banks * Feature : 1,375mil height & double sided component * Refresh : 4K/64ms * Contents ; Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 10ns 6ns ECC PC100 Unbuffered DIMM Function Supported -1H 128bytes 256bytes (2K-bit) SDRAM 12 10 2 Rows 72 bits LVTTL 10ns 6ns A0h 60h -1L -1H Hex value -1L 80h 08h 04h 0Ch 0Ah 02h 48h 00h 01h A0h 60h 02h 80h 08h 08h 01h 8Fh 04h 06h 01h 01h 00h Note 1 1 2 2 15.625us, support self refresh x8 x8 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 10ns 6ns 20ns 20ns 20ns 50ns 12ns 7ns 20ns 20ns 20ns 50ns A0h 60h 00h 00h 14h 14h 14h 32h 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time 0Eh C0h 70h 00h 00h 14h 14h 14h 32h 20h 20h 10h 20h 20h 10h 20h 2 2 2 Rows of 128MB 2ns 1ns 2ns 2ns 1ns 2ns Rev 0.1 Apr. 2000 SERIAL PRESENCE DETECT Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, # of banks in Comp. & interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations 1 H Blank 0 -1H 1ns - PC100 Unbuffered DIMM Function Supported -1L 1ns -1H 10h 00h 12h 29h CEh 00h 01h 4Dh 33h 20h 37h 34h 53h 33h 33h 32h 33h 43h 54h 30h 2Dh 43h 1 L 31h 48h 20h 30h 43h 64h FFh FDh 5 3 3 4 5 31h 4Ch 59h Hex value -1L 10h Note PC100 SPD Spec. Ver. 1.2A Samsung Samsung Onyang Korea M 3 Blank 7 4 S 3 3 2 3 C T 0 "-" C C-die (4th Gen.) Undefined 100MHz Detailed 100MHz Information Undefined Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung s own purpose. Rev 0.1 Apr. 2000 |
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